CISC vs. RISC
P.J. Drongowski

References.

  Reduced instruction set computers, David A. Patterson,
  CACM, Vol. 28, No. 1, January 1985.

  VLSI processor architecture, John Hennessy, IEEE Trans.
  on Computers, December 1984.

von Neumann performance bottleneck -- the Pc-M channel.

  * All addresses, instructions and data must pass through
    the channel.
  * Transfer and access rates must be balanced between
    the processor and memory.
  * Performance improvement measures either increase the
    Pc-M transfer rate or reduce information flow through
    the channel.
    + Keep more information in the general registers.
    + Add a DMA channel for fast, bulk I/O.
    + Use a cache memory in the processor.
    + Put more function into microcode.

Cache memory.

  * Can be modeled (or implemented) using a content
    addressable memory (CAM.)
  * Address is stored with data item and is used to retrieve
    that item during a read operation.
  * Cache must be kept consistent with primary memory.
    + Write-through cache implementation.
    + DMA I/O must invalidate cache data.

        ---------------------------------
        |  Address   |  Data  |  Valid  |
        |   field    |  item  |   bit   |
        ---------------------------------

Complex instruction set computers.

  * More function per instruction.
    + Microprogramming permits arbitrarily complex instructions.
    + Fewer instruction fetches (memory reads) are required.
    + Microcode executes faster than regular machine instructions.
      (This was especially critical when primary memory was
      much slower than the processor, e.g., core technology.)
  * Higher level language support in hardware.
    + Conjecture: Compiler construction for register machine is difficult.
    + Conjecture: Stack or M-M architectures are better target machines.
  * Close the semantic gap between HLL constructs and the hardware.
  * Improve memory efficiency by reducing the number of instructions
    per program, i.e., shrinking the program size.

CISC principles (mid-1970's technology.)

  * Control store technology (primarily ROM's) permitted large,
    inexpensive control stores. (And microprograms grew.)
  * Moving software functions to microcode made computers faster.
  * Execution speed was proportional to program size. Thus, smaller
    programs led to faster computers.
  * Memory-to-memory and stack architectures were the preferred
    execution models.

Example -- VAX-11/780.

  Year: 1978
  Number of instructions: 303
  Control memory: 480 Kbits
  Instruction sizes (bits): 16-456
  Technology: TTL MSI
  Execution model: R-M, M-M, R-R
  Cache size: 64Kbit

Copyright (c) 1986 Paul J. Drongowski