PDP-11 architecture P.J. Drongowski What made the PDP-11 competitive? + Low cost (for its time.) + Relatively easy interfacing for control and lab applications. + Small size (PDP-11/20: 19" wide by 10" high.) + General register machine (relatively easy to program.) + 16 bit data word and address. + Easy character handling (byte addressability.) + UNIBUS was a flexible I/O bus. Drawbacks. + 16-bit address became too small. + UNIBUS was too slow. + 32-bit integers are more useful in practice. + Low floating point throughput. - 32-bit parallel transfers needed. - Poor floating point accelerators. Major competitor -- the Data General NOVA. + 16-bit machine with 4 registers. + Word addressable machine. + Somewhat baroque ISA (Kind of a 16-bit PDP-8.) UNIBUS + Processor uses same signals to communicate with memory and peripheral devices. + Processor registers, memory and I/O devices are all assigned addresses on the UNIBUS. + Device registers are manipulated like memory addresses. ________________________________ | | | ooooo | CPU Memory I/O I/O + Signaling. - Bi-directional. - Byte and word transfers are permitted. - Master/slave relationship. * At any one time, there is a bus master controlling the bus. * The master asserts control over the slave. * Typical situations: + Processor to/from memory (instruction fetch and execute.) + Disk to/from memory transfer (DMA.) - Asynchronous (interlocked communication.) * Every control signal issues by master must be acknowledged. * Communication is independent of bus length. * Transfer time depends upon duration of M/S dialog. * Synchronization with central clock is eliminated. - DMA devices are given highest priority, preventing the CPU from locking out devices. + Interrupts. - Every device has a trap vector. * Two word location in the first 1K or so of memory. * First word is new PC, second word is new PS. - Interrupt sequence. * Old PC and PS are pushed on stack, then new PC and PS are loaded. * Forces processor to execute a routine to handle the interrupt or exception condition. - Since every device has its own trap vector, the processor does not have to poll the devices to find out which one caused the interrupt. Programming. Data types. Byte (character) 8 bits Two's complement Signed integer 16 bits Two's complement Unsigned (address) 16 bits Positive magnitude Floating 32 bits Excess 128 exponent Double floating 64 bits Excess 128 exponent General registers. R0 - R5 General purpose R6 Stack pointer R7 Program counter Processor status word (PSW.) 15:14 Current mode 13:12 Previous mode 7:5 Processor priority 4 Trace | 3 Negative | 2 Zero | Condition codes 1 Overflow | 0 Carry bit | Memory. + Byte addressable machine. + Top 4K words are reserved for device registers. Address modes. 0 Register R 1 Register deferred (R) 2 Auto-increment (R)+ 3 Auto-increment deferred @(R)+ 4 Auto-decrement -(R) 5 Auto-decrement deferred @-(R) 6 Indexed X(R) 7 Indexed deferred @X(R) Program counter (R7) modes. 2 Immediate #N 3 Absolute @#A 6 Relative A 7 Relative deferred @A PDP-11 instruction set. + Double operand instructions. + Single operand instructions. + Jump and subroutine group. + Condition code group. + Trap and interrupt. - EMT - TRAP - BPT - IOT - RTI - RTT (May not be implemented on all 11-series machines.) + Miscellaneous. - HALT - WAIT - RESET Trap and interrupt instructions. SPL - set priority level. + PS<7:5> <- priority. + Priority is specified in three least significant bits of the instruction. EMT - emulator trap. + Opcodes 104000 : 104377 + Trap vector 30 (octal) + Operation: -(SP) <- PS -(SP) <- PC PC <- (30) PS <- (32) + Used for operating system calls. TRAP - user trap. + Op codes 104400 : 104777 + Trap vector 34. BPT - breakpoint trap. + Trap vector 14. + Used for debugging and building debuggers. - Put BPT in middle of program. - Trap to debugger when executed. IOT - input/output trap. + Trap vector 20. + Originally used in paper tape software and DOS. RTI - return from interrupt. + Exit from interrupt or TRAP service routine. + Operation: PC <- (SP)+ PS <- (SP)+ Miscellaneous instructions. HALT - halt processor and enter console routine. WAIT - wait for interrupt. + Processor does not compete for UNIBUS. RESET - Send INIT on UNIBUS. + Puts devices into power up state. Exception conditions. + Error conditions which are detected and reported by hardware. + On the PDP-11, an exception will cause a trap. + Traps have a priority in case more than one error occurs at once. Order is implementation dependent. + Exceptions: - CPU (bus) error (trap location 4.) * Illegal instruction. * Illegal addressing mode. * Odd addressing error. * Bus time out. + No response from location on the bus. + Probable cause -- non-existent memory or peripheral device. - Reserved instruction (trap location 10.) - Power fail (trap location 24.) * AC power drops below 95V. * Line frequency outside 47 to 63 Hertz. * Two msec to save volatile information and prepare peripherals for power failure (e.g., retract disk heads.) * When power is restored, processor traps to 24 to restart computation. - Memory system errors (114.) * Parity error. * Uncorrectable memory error. - Floating point error (location 244.) * Some errors must be enabled in the FPP status register. * FPP exception register must be checked after trap. * Undefined variable (indicated by -0.) * Underflow. * Overflow. * Integer conversion error. * Divide by zero. * Floating opcode error. Copyright (c) 1986 Paul J. Drongowski