Technology P.J. Drongowski Computer Engineering: A DEC View of Hardware Systems Design, C.G. Bell, J.C. Mudge, and J.E. McNamara, Digital Press, 1978 The fundamental principle of computer architecture. "Technologies dictate the kinds of structures that can be considered and thus come to shape our whole view of what a computer is." (Bell and Newell 1972) Generations of computer (by logic technology) Period Technology ------ ----------- 1945 - 1958 Vacuum tubes 1958 - 1966 Transistors & core 1966 - 1974 Integrated circuits 1974 - Present Large scale integration Future VLSI Magnetic core memory > Non-volatile. > Random access. > Storage mechanism. + Toroid of ferromagnetic material. + Wires run through the toroid (core.) + Passing current through wire creates magnetic flux. + Direction of flux depends upon the direction of the current. One direction is 0, the other is a logical 1. + Flux remains after current is turned off. + A sense wire also passes through the core. Current is passed through the drive wire in the same direction as a logical zero. If a one was stored, the flux reverses and a voltage is induces on the sense wire. + Read operation is destructive, so information must be written back. Semiconductor memory. > Dynamic: MOS gate capacitance as storage device. > Static: Bistable device. Development/production costs. > System life cycle. + Development (Non-recurring.) + Manufacture (Recurring.) + Maintenance (Customer.) > Cost and price. + Amortization of non-recurring costs. - Higher A-rate increases price. - Higher volume decreases A-rate. - Decrease development cost by increasing designer productivity. + Recurring per unit costs. - Time, material, labor, etc. - Decrease by shrewd engineering and management. System level product costs. > Mechanical. + Pin, package, board, backplane, cabinet. + Increase functionality per unit space. > Cooling + Convection, forced air, liquid. + Maximize "bang per watt." > Power. > Interconnection. > Maintenance. + Maximize availability. + Fault isolation. + Replace or repair. Why VLSI? > Mechanical. + More functionality per package. + Fewer packages, smaller/fewer boards, etc. > Interconnection. + Less board level interconnect. + Lower wire capacitance, higher speed. + Interconnect problem moved to chip design. > Power supply. + Lower wire capacitance + Less power to charge and discharge wires. > Cooling. + May require special packaging/cooling. > Maintenance. + Chip replacement strategy. + Fewer parts, greater reliability. > Other opportunities. + Due to volume, many Pc's & M's can be configured. + Logic enhanced memories. Customization hierarchy % of wafer Development Prototype Technology pre-processed cost/chip lead time Full custom 0% $50K-$250K 9-18 mo Standard cell 0% $30K-$90K 4-6 mo Macro cell 80% $15K-$40K 3-4 mo Gate array 80-90% $5K-$20K 1-2 mo Fuse programmable 100% None Shelf Gate arrays. > Predefined core of gate templates. > Core is surrounded by interface circuits and bonding pads. > Gate templates programmed by 1 or 2 metal mask layers. > Applications. + Replace random logic. + Glue logic. + Short fuse projects (fast turnaround.) + Low volume. Standard cells. > Pre-designed logic circuits. + Stored in computer-based library. + PLA's, RAM, ROM, microcomputers. > Chip area is uncommitted. > Placement and routing may be automated. > Applications. + Controllers. + Moderate volumes. + Higher density than gate arrays. + Longer development schedule. Full custom. > Chip area is totally uncommitted. > Design primitives. + Transistors. + Wires. + Some pre-defined library circuits. > Applications. + Very high density. + Maximum design flexibility. + Long development schedule. + High volume. Copyright (c) 1986 Paul J. Drongowski