Input/output Buses
P.J. Drongowski

References.

  Computer Engineering ...... Chapter 11, "Buses, The
  Skeleton of Computer Structures.


Bus - General requirements.

  * Does the bus establish the communication pathway required?

  * Is the bus well-specified so that interfaces may be designed
    concurrently or over a period of time by different engineers?

  * Does the bus avoid imposing unnecessarily strict performance
    constraints on the system?

  * Is the cost of the bus and its connections commensurate
    with the computer system and the bus' role in it?

  * Can the bus be manufactured and tested in high volume
    production without excessive hand-crafting or tuning?

Expansion and technology.

  * Expansion.
    + Bandwidth may become inadequate.
    + Addressing may become a limitation.
    + UNIBUS.
      - Processor-memory speeds surpassed UNIBUS bandwidth.
        > Transfer rate: 21.3 Mbyte/sec or 1 word per 0.75 usec.)
        > Semiconductor memory speed is less than 300 nsec.
      - 18-bit memory address width became a limitation.

  * Technology.
    + Bandwidth/cost is relatively steady.
    + Bus designs tend to persist in time across redesigns.
    + Initial design is, therefore, quite important.

How busses are designed.

  * Identify the system components to be interconnected.
  * Study the communication requirements.
  * Choose a structure and protocol.
  * Use cost constraints and available technology to
    guide the implementation.

                               Communications-------External
                               Controller
                                |
    Pc--------------------------|
     |            |             |
     |            |            Terminal
     |           Disk          Controller
     M-----------Controller     |
                  |             |-----------Terminal
                  |             |
                 Disk           |-----------Terminal
                                |
                                |-----------Terminal

Five function model of computer busses.

  1. Processor to memory interconnection.
     + Function: Transfer instructions and data.
     + One address is required per word transferred.

  2. Memory to secondary (bulk transfer) I/O controller.
     + Function: Block mode, direct memory access transfers.
     + One address per block is required; words are stored in
       consecutive memory locations.

  3. Processor to I/O controller.
     + Function: Control pathway.
     + Characteristics.
       - I/O commands sent from CPU to I/O controllers.
       - Status information returned from controllers to CPU.
       - I/O controllers can interrupt processor.
       - Small, low speed data transfers permitted (e.g.,
         console terminal.)

  4. I/O controller to peripheral.
     + Function: Carry information from peripheral to controller.
     + Characteristics are very sensitive to nature of I/O device.

  5. I/O controller to external communication lines.
     + Examples: RS-232C, Ethernet, etc.
     + Characteristics may be set by some other standard.

Five key bus requirements.

  * Memory addressing.
    - Address per word vs. address per block.
    - Separate busses for each type permits higher speed.
  * Maximum number of connections.
    - Number of signals required to select a destination.
    - N signals are sufficient for 2^N connections.
  * Latency tolerance. Maximum tolerable delay from the start
    of the transfer to completion.
  * Bandwidth. Complete transfers per second.
  * Length.
    - Maximum distance from one connection to another.
    - Affects both cost and performance of bus.
    - Processor to memory bus.
      + Speed of signals along bus determines relationship
        between length and latency.
      + Pc-M lengths have been shrinking to reduce latency
        and increase transfer speed.
      + CPU's and memory are usually packaged in close proximity.
      + Typical length for minicomputers: 0.1 to 3 meters.
    - Controller to memory busses.
      + High speed block transfer I/O controllers also tend to
        be packaged closer to memory.
      + More controllers may be required, however. Bus lengths
        are 2 to 10 times longer (0.2 to 30 meters.)

Bus taxonomy and characteristics.

                    Pc-Memory  K-Memory  Pc-K     K-Device  K-External

Memory address      > 2^22     > 2^22    N/A      N/A       N/A

# of connections    16         16        64       256       256

Latency tolerance   500 nsec   50 usec   5 usec   5-50 usec 5-50 usec

Bandwidth           5 Mb/sec   1.2 Mb/s  0.1 Mb/s 0.1-5 M/s 0.1-5 M/s

Length              3 meters   30 meters 30 meters < 300 m  < 1 Km


Two basic types of transfer protocol.

  > Synchronous.
  > Asynchronous.

Synchronous busses.

  > High speed.
  > Typically used for tightly coupled communications such as
    Pc-M or Controller-device transfers.
  > Timing diagram.
           - - - - - -  -----------------------
       Data           \/
           - - - - - -/\-----------------------
                                  _______
      Clock______________________|       |_____

                       <--Setup--><-Hold->
                          Deskew
  > Deskewing.
    + Signals must be stable on data lines before clock is asserted.
    + Set-up time must include deskewing time and logic setup time.
    + Thus, bus timing depends in part upon the bus length.
    + Bus length may require tuning to obtain a working system.
    + If these timing assumptions are violated, the bus will fail.

Asynchronous busses.

  > Lower speed because more signaling is required per transfer.
  > All signals must be acknowledged -- interlocked operation.
  > Timing diagram (4-cycle handshake.)
                       ______________
          Request_____|              |____________
                             ______________
      Acknowledge___________|              |_______
                 
                 - - - - - - -   ------------------
             Data              \/
                 - - - - - - - /\------------------

  > Protocol is independent of bus length. Fewer assumptions
    are made about timing.

Self-timed systems (optional.)

  > Equipotential regions.
  > Local clocks.
  > Asynchronous handshakes between regions.

Copyright (c) 1986 Paul J. Drongowski