Input/output control models
P.J. Drongowski

Program directed control.

  > Earliest model for I/O.
  > All transfers are performed through the CPU.
  > No concurrency. The Pc is slowed down to device speed.
  > Sequence (block transfer.)
    1. Select I/O device.
    2. Loop until ready.
    3. Transfer word from I/O buffer to accumulator.
    4. Transfer accumulator contents to memory location.
    5. Update memory pointer.
    6. If block transfer is not complete, go to step 2.
    7. Disable the I/O device.
  > Illustrate using the PDP-11.

Concurrent I/O model.

  > Assume a direct memory to device transfer capability.
  > A mechanism is required to inform the Pc that a transfer
    is complete or has been aborted due to an error.
  > Polling.
    + When idle, the Pc checks the I/O devices to determine
      which ones are busy or ready.
    + Polling can be performed on a periodic basis as well.
      (Example, terminal front-end or crossbar.)
    + Polling is often used in systems with a large number
      of terminals such as an airline reservation system.
    + The processor may not always be idle or have sufficient
      capacity to poll and compute.
  > Interrupts.
    + Device communicates with the processor only when necessary.
    + Questions to be answered (architecture checklist.)
      - When is an interrupt recognized?
        * Recognition point must be clearly defined.
        * Recognition at the beginning of instruction fetch
          is the obvious choice.
        * Interrupt request can be latched into a F/F.
          The processor tests the state of the F/F.
        * Special cases.
          + Microprogramming: branch logic is needed.
          + Complex instructions: How long can an interrupt wait?
          + Pipelining: What should the Pc do with partially
            executed instructions?
      - What is the source of the interrupt?
        * Determine the interrupt priority: chaining vs. scanning.
        * Determine device: polling vs. interrupt vector.
        * Processor must acknowledge interrupt and lock out other
          interrupts.
      - What actions must be taken to clear it? (Device service routine.)
      - How is execution of the interrupted program resumed?

Interrupt systems.

  > Single level, single priority.
    + All interrupt lines are OR'd into a single F/F.
    + Control transfers to a single location.
    + Service routine polls devices.
    + Polling order determines priority.
  > Single level, multiple priority.
    + Request flip/flops are daisy chained.
    + Order in chain determines priority.
  > Multiple level, single priority.
    + Devices transmit select code to processor when all previous
      interrupts have been acknowledged.
    + Service routine determines if current interrupt can be preempted.
  > Multiple level, multiple priority.
    + Hardware preemption.
    + Mechanism: daisy chain plus masking.

Copyright (c) 1986 Paul J. Drongowski