VLSI systems #11
Architecture and methodology revisited
P.J. Drongowski

Five different representations for a VLSI design.
  Architecture		What to compute.
  Organization		How to compute it.
  Logic			Logic level implementation of building blocks.
  Electrical		Electrical behavior of logic/building blocks.
  Geometry		Layout.

First part of the course.
  * Specification of an MSI complexity logic circuit.
  * Electrical characterization of its behavior.
  * Circuit layout.

Issues in design/complexity management at the circuit level.
  * Representations.
    + Electrical.
      - Terms.
	# Enhancement transistor.
	# Depletion transistor.
	# Wire (series resistor, parallel capacitance.)
 	# Circuit inputs/outputs.
      - Composition rules.
	# Pull up.
	# Switch (Charge transfer.)
	# Memory (Charge storage.)
	# Restoring logic (Charge amplification.)
      - Constraints.
	# Power gain >= 3.
	# No shorts from Vdd to ground.
    + Geometry.
      - Terms.
	# Layers = { Poly, Diff, Implant, Buried, Contact, Metal, Glass }.
      - Composition rules.
	# Enhancement transistor.
	# Depletion transistor.
	# Wire.
        # Circuit inputs and outputs.
      - Constraints.
	# Geometric design rules.
	# Distribute Vdd and ground on metal.
	# Maximum current density on metal supply wires.

Interrelationships between electrical and geometric representations.
  * Arrangement of semiconductor materials maps up to electrical circuit.
  * Electrical circuit maps down to geometry.
  * Descriptions must be consistent.
    + Same transistor sizes.
    + Same R's and C's for wires.
    + Interconnection of sources, drains, gates, inputs and outputs
      must be identical.

Small is easy.
  * Interrelationships are easily managed without automation for
    small (40-50 transistor) circuits.
  * Behavior is easily specified.
  * Semantics are similar between electrical and geometric representations.

Second part of the course.
  * Specification of system architecture.
    + Hardware processes.
    + External interfaces.
    + Speed, space and power constraints.
  * Translation of architecture to organization (building blocks.)
    + Decomposition to regular building blocks and microcode.
  * Interconnection and simulation of system at organizational level.
    + Translate building blocks to logic circuits.
    + Simulate with RSIM.
  * Tracking technology dependent constraints through design process.

Issues.
  * Allocating space and power to achieve performance.
  * Inter-representation semantics.
    + Incompatible representations, especially between organization
      and logic levels.
    + Problems are 1000-10000 times larger in scale -- more
      complexity to manage.
  * Partitioning a system across chip boundaries to achieve the best
    S/S/P mix.

Given a design with 100,000 transistors, can you:
  * Verify that it is correct wrt its specification?
  * Can you test circuits against the spec?
  * Will it produce a timely result?
  * Floor planning and circuit size.
    + Will it fit onto a 6500 by 6500 micron die?
    + Can the building blocks be interconnected?
    + Can power, ground and the clocks be distributed easily?
    + How will wire length affect performance (delays?)
  * Can power dissipation be held to 2 watts?
  * Will 24, 40, 64, or more pins be required?

Copyright (c) 1984 Paul J. Drongowski