VLSI Systems #13
N.mPc organization level descriptions
P.J. Drongowski

> Interpretation of restricted ISP' descriptions. (Can an ISP'
  description be written that captures the datapath structure?)

  + State. Instance of a register or register file.
  + Function. Instance of a combinatorial circuit.
  + Register transfer.
    - Destination structure. Signal sink.
    - Source structure. Signal source.
    - Function call. Presence of combinatorial circuit on path.
  + Structures as function parameters. Signal sources connected to
    function inputs.
  + Function result. Signal source from combinatorial circuit
    to signal sink.
  + Ports. External signals.
  + When process. Locus of control for hardware unit.

> Present ISP' example given below.

> Problems.
  + More than one output from a function (combinatorial circuit.)
  + Cannot efficiently model purely combinatorial circuits.
    Every when process has an execution context (i.e., local state,
    stack, etc.) Switching from one process context to another is
    an expensive operation. Use the NAND gate example given below.

	port A, B, Nand;	/* Inputs and output */

	when (A) := ( Nand = A nand B; next )
	when (B) := ( Nand = A nand B; next )

  + More exotic next address logic may be necessary. (Memories
    are sufficient for ROM-based microcode -- not necessarily good
    for PLA's which are essentially combinatorial functions.)

/*
 * Micro-engine example.
 */

/*
 * Author:  Paul J. Drongowski
 * Address: Computer Engineering & Science
 *          Case Western Reserve University
 *          Cleveland, Ohio 44106
 * Date:    November 9, 1983
 *
 * Copyright (c) 1983 P.J. Drongowski
 */

/*
 * PLA-based controller with an LSSD micro-instruction register.
 * Datapath is a register file feeding one input of an ALU. The
 * output of the ALU is sent to an accumulator register. The register
 * output is fed through a byte-swapper to the other input of the
 * ALU.
 */

port    Clock< 0 >,                 /* External clock line */
        Reset< 0 >;                 /* External reset line */

state   Mir = < 0:15 >,             /* Micro-instruction register */
        Reg[ 0:15 ]< 15:0 >,        /* Register file */
        AC< 15:0 >;                 /* Accumulator */

memory  Mstore[ 0:31 ]< 0:15 >;     /* Microcode store */

format  Iac   = Mir< 0 >,       /* AC enable */
        Iop   = Mir< 1:3 >,     /* ALU operation */
        Iin   = Mir< 4 >,       /* ALU carry in */
        Iswap = Mir< 5 >,       /* Swap enable */
        Ireg  = Mir< 6:9 >,     /* Register file address */
        Ien   = Mir< 10 >,      /* Register write enable */
        Iaddr = Mir< 11:15 >;   /* Next instruction address */

/*
 * Macro definitions.
 */

macro   LO = 7:0 &,
        HI = 15:8 &;

/*
 * Swapper model.
 */

function Swapper

    (
    Value< 15:0 >,      /* Operand input */
    Enable< 0 >         /* Swap enable control input */
    )

    < 15:0 > :=         /* Result */

    (
    Swapper = Enable => ( Value<LO> concat Value<HI>) else Value
    )

/*
 * ALU model.
 */

function ALU

    (
    A< 15:0 >,     /* A (left) operand input */
    B< 15:0 >,     /* B (right) operand input */
    Op< 0:2 >,      /* Operation */
    In< 0 >         /* Carry in */
    )

    < 15:0 > :=     /* Result */

    (
    ALU =
        case Op
            0: 0
            1: not B
            2: A and B
            3: A or B
            4: A xor B
            5: A + B + In
            6: A - B - In
            7: 0177777
        esac
    )

when (Clock : lead) :=

    (
    if (Iac) AC = ALU( AC, Reg[ Ireg ], Iop, Iin );
    if (Ien) Reg[ Ireg ] = Swapper( AC, Iswap );
    Mir = Mstore[ Iaddr ]; next
    )

when (Reset : lead :=

    (
    Mir = 0; next
    )

Copyright (c) 1984 Paul J. Drongowski