VLSI Systems #14
Testing
P.J. Drongowski

Multilevel test strategy.

  * Operational test.
    + Health and status checking during operation.
    + Implemented in software.
    + Detect and report "hard" and "soft" errors.
    + May handle only relevant (application oriented) conditions
      to keep system overhead low.
  * Non-operational mode diagnostics.
    + Off-line health test.
    + Implemented in software.
    + Actively exercise hardware to induce errors.
  * Hardware self-test.
    + Implemented in microcode and hardware or via RAM in
      test fixture.
    + Data and control path checkout at machine speed.
    + May require additional hardware for test pattern generation.
      - Generate test pattern via linear feedback shift register (LFSR.)
      - Eight or more latch positions.
      - Produces a pseudo-random number every clock cycle.
      - LFSR can be used to compress test results into a signature.
    + Test result reported via register probes.
  * Quality assurance test.
    + External.
    + Functional testing.
      - Test vectors driven into device and response recorded.
      - Requires additional hardware such as probe points, LSSD.
    + Electrical and parametric testing.
      - Performance over supply ranges.
      - Performance over temperature range.
      - Input/output voltage levels (under load.)
      - Delays within acceptable limits.
    + Ad hoc (bus structured) approach.
      - Set up/observe registers via busses.
      - Load/read procedure may be different for each register.
      - Usually uses manually generated test patterns.
    + Structured approach.
      - Control/observe memory elements in race-free manner.
      - Procedure reduces to combinatorial logic test.
      - Level-sensitive Scan Design (LSSD.)

Signature analysis.

  * If a working part is stimulated with a particular sequence of
    test data, it will always produce the same (correct) result.
  * To reduce the volume of data to be examined, the results can
    be compressed using an LFSR (a shift register with an XOR gate
    in the feedback loop.)
  * A signature is an N bit quantity which is the compression of
    the test data.
  * By comparing the signature of the device under test with the
    expected signature of a working part, a defective part is easily
    detected since its signature will be different.
  * Computing a signature is exactly analogous to computing a
    a software checksum!

LFSR picture.

  * Three latches.
  * XOR feeding input of each latch.
  * Other input of XOR comes from logic network.
  * Outputs of Latches can be applied to another logic network.
  * Feedback to first XOR from last two latch outputs through
    another XOR.
  * Can both generate patterns and compress results.

Every level of test adds another measure of confidence in system
correctness. Higher levels may reliably depend upon lower levels
to guarantee performance (within some constraints) such that higher
level checks will be valid. Quality of test results depend upon
accurate models for device behavior. Machine processable models
make automatic test generation techniques possible.

Factors affecting design for testability (optional.)

  * Degree of fault coverage.
  * Ease of obtaining patterns.
  * Effect on computer cost and scheduling.
  * Type of tester to be used.
  * Possible uses of structure at system level.

Level Sensitive Scan Design.

  * Level sensitivity. Independent of internal circuit delays and
    primary input skew.
  * Scan design. Auxiliary mode in latches to clock bits in and out.
  * Polarity hold latch.

	L  = Y
                        _
	Y' = CD + YD + YC

  * Two polarity hold latches make up a shift-register latch.

Fault insertion -- an ally to testing.

  * Use model of system to find faults.
  * Try to make model fail in same way as real system.
  * Insert "stuck-at" faults into model.

Test project (thesis opportunity.)

  * Tektronix Digital Analysis System (DAS.)
    + 32 channel pattern generator at 25 MHz.
    + 32 channel data acquisition module to 25 MHz.
    + RS-232 download for remote programming.
  * Combine DAS with Apollo to generate test programs,
    capture, playback and compare results.
  * External control over clock, tri-state inhibit, PAUSE
    or INTERRUPT.
  * Pattern generator instructions.
	COUNT	Count from X to N where N <= 256
	REPEAT	Repeat data pattern this step N times
	HOLD	Hold output at the step for N clocks
	HALT
	GOTO	Branch
	CALL	Jump to subroutine
	RETURN	Return from subroutine
  * Clock control.
    + Split clocking.
    + Multiple clock qualifiers.
    + Synchronous/asynchronous operation.
  * Trigger modes.
    + Word A (N) times.
    + Word A followed by word B.
    + Word A then not word B.
    + Reset on word C.

Sampling and testing (optional.)

  * Production run yields devices whose performance is
    statistically distributed, i.e., some run faster than
    others.
  * If performance is broken down into classes, there will
    be some devices in each performance class.
  * Usually there are more devices in lower performance classes.
    Hence, lower performance devices are less expensive.
  * The testing procedure determines whether a part is marked "high
    performance" or "low performance." The parts do not really
    differ in design!

Copyright (c) 1984 Paul J. Drongowski