VLSI systems #15
Synchronization failure and self-timed systems
P.J. Drongowski

**********
Clock skew
**********

There are two kinds of clock skew.
  * The parasitic capacitance that a wire induces on the output of
    a logic circuit.
  * The rate at which the voltage driven into a wire will equalize
    across the length of the wire -- the diffusion delay.

Diffusion delay is determined by the resistivity and capacitance
of a wire. It is independent of wire width since a wider wire has
a lower resistance, but a higher capacitance. Diffusion delay is
roughly quadratic with the length of the wire.

Poly and diffusion have a high resistance and capacitance. Hence,
the diffusion delay on these wires is fairly high. Assuming a 10mm
wire, the diffusion delays for poly, diffusion, and metal are
about 200 nsec, 100 nsec and 0.1 nsec, respectively. Resistance
goes up as wire width scales down.

Diffusion delay is a problem for clock distribution. Consider
the two cases in which several data lines and one clock line are
routed around a corner. (In one case, the clock is on the inside
track and in the other case, it is on the outside.) The clock
skew will be much greater for the outside track! Hence, clock
delay (skew) is topology sensitive and it will ultimately
limit the performance of the system.

***********************
Synchronization failure
***********************

			  -------
      Asynchronous -------|	|
	     Input	  |   Q |------ Output
		      ----|>	|
		      |   |	|
		      |	  |	|
		  Clock	  -------

If we attempt to capture the value of an asynchronous signal
with a D flip/flop, can we anticipate any problems?

  * If the F/F was a perfectly discrete device, the input
    would also be synchronized successfully.
  * However, real world devices and signals are NOT discrete.
    (Historical note. There was a period where devices were
    thought to be discrete. It's just that computational events
    took so much time, that the rise and fall times were
    "insignificant.")
  * Every device must switch through a transition region
    where no information is present. (The "no information"
    state is recognized in software, too. It is "bottom" in
    fixed point theory, or just a plain old uninitialized
    variable.)
  * Most "synchronization" schemes merely postpone failure.
  * Use a stoppable clock instead. Do not allow a synchronous
    system to sample its inputs unless valid data is present.

******************
Self-timed systems
******************

Banish the notions of "absolute time" and simultaneity.
  * Simultaneity in a physical system simply does not exist.
    (Uncertainty principle, perhaps?)
  * One can only define a window in time during which two
    events might be said to be "concurrent."

An equipotential region relates the notion of distance
(and diffusion delay) to time. An equipotential region
is a spatial region in which all diffusion delays are
within some acceptable window or limit.

A self-timed system is a system within an equipotential
region which keeps its own notion of "absolute" time.
Absolute global time does not exist. One can only define
a partial order on global events (e.g., event A precedes
event B.)

Architectural implications.
  * Local clocks are OK as long as they control events within
    a particular equipotential region.
  * 4-cycle signaling should be used to exchange information
    between two equipotential regions.
  * Self-timed systems can increase the parallelism in a system.

Self-timed systems are the hardware equivalent of asynchronous,
co-operating software processes.

Double rail signaling (optional.)

Copyright (c) 1984 Paul J. Drongowski