VLSI systems #16 Architectural topics P.J. Drongowski Interconnect to gate cost ratio cost/wire --------- cost/gate 1946 100KHz switching speed ~ 10 usec gate I:G cost ratio ~ $0.01 / $10.00 I:G delay ratio ~ 3 nsec / 10 usec 1983 100MHz switching speed ~ 10 nsec gate On chip wires: I:G cost ratio ~ $0.001 / $0.001 I:G delay ratio ~ $0.001 / $0.001 Off chip wires: I:G cost ratio ~ $0.01 / $0.001 I:G delay ratio ~ 10 nsec / 10 nsec Observations. * Active logic is cheaper. * Off chip wires are getting more expensive relative to active logic. * Going off chip is more expensive than staying on chip in both production cost and signal delay. von Neumann computer structure. IO.programmed ----- Pc ------ M.primary | | --------- IO.dma Data model. M.primary is a linearly addressable array of homogeneous fixed length data units (words.) Execution model. forever IR <- M[ PC ] PC <- PC + 1 Execute (IR) repeat Observations. * Instruction fetches need over 50% of the available memory bandwidth. * Memory management is always a problem. * Data structures must be mapped to the linear array, fixed length word memory model. Dataflow execution model. * When operands are available, execute the instruction. * This is equivalent to a bipartite dataflow graph. * Content addressable memory can be used to find fireable instructions. * Communication of operands and results becomes a major problem. (Try trees?) * Translate algorithm (graph) directly to silicon? (Self-timed implementation.) Reduction engine model. * Substitute operands for formal parameters. (Lambda calculus.) * Evaluate expression on a tree machine. * What can I/O or storage be implemented on such a machine? Systolic arrays. * Information pumps through array of processors. * Supports both spatial and pipelined concurrency. * Good for algorithms with high degree of regularity. Outstanding problems with alternatives. * Communications. * Implementation of database or long term store. Copyright (c) 1984 Paul J. Drongowski