VLSI Systems #3
MOS transistors
P.J. Drongowski

******
Solids
******

Solid matter can be assigned one of three classifications.
  1. Insulator. Valence electrons are tightly bound to nuclei.
     An insulator does not readily conduct charge.
  2. Conductor. Valence electrons are easily separated from
     their atoms. Adding "extra" electrons to a conductor will
     easily displace electrons out the other end.
  3. Semiconductors have a behavior somewhere in between.

Silicon.
  * Insulator.
  * 4 valence electrons.
  * Bonds covalently with 4 neighbors.

N-type material.
  * Doping with phosphorous produces n-type material.
  * Phosphorous has 5 valence electrons.
  * After forming 4 covalent bonds, one extra electron will be
    free in the lattice.
  * The extra electron creates an ionized site with a net
    negative charge.

P-type material.
  * Boron dopant.
  * Boron has 3 valence electrons.
  * Three covalent bonds will be formed.
  * The hole creates an ionized site with a net positive charge.

****************
nMOS transistors
****************

Draw the cross-section for an nMOS transistor showing the gate,
source and drain regions. Also, draw a schematic symbol for an nMOS
enhancement transistor.

"nMOS" is an acronym for "n-channel metal oxide semiconductor."
It describes the "sandwich" of materials that form an nMOS
transistor.
  * Metal.
    + Originally used for transistor gates.
    + Power distribution and low resistance interconnections.
    + Aluminum.
  * Oxide.
    + Silicon dioxide insulator.
    + Thin oxide layer is used as gate insulator.
    + Thick oxide separates other layers.
  * Semiconducting materials.
    + Substrate.
      - Wafer base for other making layers.
      - p-type material.
      - Body of the transistor.
    + Polysilicon.
      - n-type material.
      - Transistor gates.
      - Highly resistive and capacitive interconnections.
    + Diffusion.
      - n-type material.
      - Source and drain transistor regions.
      - Highly resistive and capacitive interconnections.

***************
Basic operation
***************

Charge.
  * All semiconductor logic manipulates charge.
  * The presence or absence of charge represents logical 1 and 0,
    respectively.

nMOS digital circuitry exploits two basic electrical effects.
  * Gate capacitance.
    + Gate, oxide insulator and substrate form a capacitor.
    + Positive charge can be applied to and retained by gate
      for a short period of time.
    + Can be used to build dynamic memories.
  * Channel conductance.
    + Channel is region under gate between source and drain.
    + Positive charge on gate repels holes in substrate under gate.
    + Charge inversion layer is formed at surface of substrate.
    + Transistors have a threshold voltage, Vth, which is set during
      fabrication. (Typical Vth = +1V for Vdd = +5V.)
    + When Vgs > Vth, the channel begins to conduct, i.e., charge
      (electrons) move from source to drain (Vds is positive.)
    + Since inversion layer is very thin (surface effect) channel
      resistance is high (order of 10^4 ohms.)
    + By switching transistors (channels) on and off, charge
      and therefore, information can be transfered from place to
      place (i.e., to and from transistor gates.)

	| Ids
	|                  *
	|                 *
	|                *
	|               *
	|             *
	|           *
	|        **
      --*********----------- Vgs
	|	Vth

Transistor behavior is affected by several factors.
  * Determined by fabrication line: Doping concentrations,
    thickness and permittivity of gate oxide, other esoterica.
  * Determined by designer: Length and width of transistor channel.

*********
Junctions (optional)
*********

    -----------------
    |   N   |   P   |
    -----------------

  * Electrons will swarm into the p-region trying to fill
    holes, i.e., sites of positive ionization.
  * Holes will be formed in the n-region as the electrons
    move into the p-type material.
  * The exchange of charges creates a depletion region at
    the junction.
  * Charge barriers eventually form and steady state is established.
    (Barriers are formed by POSITIVE phosphorous and NEGATIVE boron
    ions that are trapped in the lattice.)

  * Forward bias.
    * Attach n-region to electron source.
    * Depletion region will narrow.
    * A large forward current will flow through junction.
  * Reverse bias.
    + Attach p-region to electron source.
    + Depletion region will widen.
    + A very small current will flow through the junction.

			| I
			|             *
			|            *
			|           *
			|          *
			|         *
			|       *
			|     *
			|  *
  ----------------------*--------------------V
		      * |
  ********************  | -I  = Saturation current
                        |   S

Copyright (c) 1984 Paul J. Drongowski