VLSI Systems #4
Circuit analysis and logic design.
P.J. Drongowski
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nMOS logic
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Operating principles.
* Represent 0 and 1 by the absence and presence of positive charge.
* Charge and discharge gate capacitors by selectively turning
(other) transistor channels on and off.
Draw picture of two transistors whose drains are connected to the
gate of another transistor. Connect the sources to +Vdd and ground.
Explain how switching one or the other of transistors on and off
will charge and discharge the gate.
Draw the equivalent low pass network. Explain that charge up and
down will be governed by RC constant for the appropriate part of
the network. Draw the voltage versus time curve for:
V(t) = Vdd(1 - exp(-t/RC ))
gate
Gate capacitance will slowly rise to Vdd-Vth, and will
quickly fall to about zero. Emphasize that rise and fall times
are asymmetric. Give equation for gate capacitance:
Epsilon x W x L
C = ---------------
gate D
where Epsilon = Insulator permittivity (0.03 pF/cm typical)
D = Insulator thickness (1000 Angstroms)
W,L = Transistor width and length
Hence, increasing the size of gate to be charged or increasing
the length of the channel through which the charge is transfered,
will increase the switching time of the circuit!
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Transit time (Optional)
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Transit time. The minimum time in which a charge placed on the
gate of a transistor will result in the transfer of a similar
charge through the channel to the gate of a subsequent transistor.
Since electrons are the charge carriers, transit time can also be
defined as the average time required for an electron to move from
the source to the drain.
2
L L L
Tau = -------- = ------ = --------
velocity mu x E mu x Vds
where mu = electron mobility
E = electric field
L = channel length
Vds = drain to source voltage
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Inverters and depletion transistors
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Resistive load.
* Use long diffusion wire for load.
* Wire must be 5000 microns long (10 ohms/square diffusion
sheet resistance, 10,000 ohm load required.)
Enhancement load.
* Draw enhancement load inverter.
* Uses high channel resistance as load.
* Explain operation for inputs of 0 (ground) and 1 (Vdd.)
* Output will only rise to Vdd - Vth.
Depletion load.
* Implant phosphorous ions into region under gate.
* Makes Vth negative (-2 volts typical.)
* Pull-ups are always turned on. Explain how this increases
power consumption.
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Restoring logic
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Motivation.
* Information is stored as energy which is slowly depleted.
* Logic circuits must have a power gain of greater than one
to restore the energy which is depleted.
* This also means we need an external power supply, of course!
Before defining "gain" we need to state the equations for Ids.
There are three important modes of operation.
Vgs < Vth Ids = 0
W Vds
Vds <= Vgs - Vth Ids = Beta --- Vds [ Vgs - Vth - ---]
L 2
W 1 2
Vds > Vgs - Vth Ids = Beta --- --- (Vds - Vth)
L 2
Draw the family of Ids vs. Vds curves for Vgs = 1, 2, 3, 4 volts.
Explain the meaning of the term "saturation." (Once Vds = Vgs - Vth,
an increase in Vds will not increase Ids.)
Define the power gain for an inverter to be the ratio of the
pull-down and pull-up currents. (Assumes that inverter drives
a logic stage which is the same size as its own.)
Ids
pd
Gain = -----
Ids
pu
Since the current flow through a transistor is proportional to
the width to length ratio of the transistor (Ids <> W/L) the
gain is set by the ratio of the ratios!
(W/L)
pd
Gain = -------
(W/L)
pu
Beware! Mead and Conway define gain in terms of the (L/W) ratios
and hence, gain is defined as:
(L/W)
pu
Gain = -------
(L/W)
pd
Draw the Vin vs. Vout transfer curve. Explain that gain is the
slope of the curve. Inverters need a gain of 3-4 to function
properly. (In terms of correct logic levels, the curve will
shift up and down, meaning that Vout may float near or above
Vth.)
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Logic design
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All nMOS logic is a variation of the inverter. Explain operation
of NAND and NOR logic.
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Design considerations
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Three questions to ask during circuit design.
1. How fast can (should) the circuit switch? (Speed)
2. How much power does the circuit require? (Power)
3. Are correct voltage levels maintained? (Noise immunity)
Copyright (c) 1984 Paul J. Drongowski