VLSI systems #6
Silicon gate nMOS process
P.J. Drongowski

Project flow.

  1. System specification.
  2. Decomposition into modules.
  3. Module design.
     a. Block diagrams.
     b. Logic design.
     c. Microcode.
     d. Layout and circuit analysis.
  4. Module integration.
  5. Fabricate.
  6. Test.

Fabrication flow (photo-lithography.)

  1. Produce pattern generator tapes from geometry.
  2. Make 10x glass reticles.
  3. Reduce, step and repeat to make 1x master masks.
  4. Print 1x submasters.
  5. Print working masks.
  6. For each mask, perform photo/processing step.
  7. Scribe, dice, mount and bond finished chips.
  8. Send packaged chips to test stage of project flow.

-> Illustrate build up of layers at the board.

Typical photo/processing step.

  * Start with a bare wafer.
  * Grow thick SiO2. (Exposure to oxygen in high temperature
    furnace. 2 hours of exposure @ 1000C grows 5000A SiO2.)
  * Cool.
  * Coat with organic resist. (0.5 to 1 micron thick.)
  * Place mask in contact with wafer.
  * Radiate exposed areas to UV light. Organic photoresist will
    break down in exposed areas.
  * Develop and remove resist.
  * Etch through SiO2 (with hydrofluoric acid.)
  * Remove resist (using chromic acid.)

Silicon gate n-channel MOS process.

  * Create sources, drains, gates and n-channel wires. [1st mask]
    + Grow thick oxide.
    + Remove oxide where sources, drains, etc. are desired.
  * Create depletion regions. [2nd mask]
    + Implant arsenic or antimony ions into exposed areas.
  * Create transistor gate insulation.
    + Grow thin oxide.
  * Create buried contacts. [3rd mask]
    + Remove thick oxide where contacts are needed.
  * Make transistors and poly wires. [4th mask]
    + Coat wafer with polycrystalline silicon.
    + Selectively remove poly leaving gates and wires.
  * Create n-type regions (self-aligning.)
    + Remove thin oxide not protected by poly.
    + Diffusion n-type impurities into substrate and polysilicon.
      Ions are driven through poly over buried contact into substrate.
      (Exposure to phosphorous at high temperature.)
  * Grow thick oxide.
  * Make contact cuts. [5th mask]
  * Create metal wires and contact covers. [6th mask]
    + Coat with metal (aluminum.)
    + Selectively remove metal leaving wires and covers.
  * Overglass. [7th mask]
    + Coat with oxide.
    + Remove oxide over bonding pads.
  * Electrical test and visual inspection.
    + Look for obvious defects (shorts, wafer flaws, etc.)
    + Probe and measure behavior of test devices.
  * Package.
    + Scribe and fracture wafer into individual chips.
    + Cement chip into package.
    + Bond wires from pads to pins.
    + Cement cover onto package.

Sources of error.

  * Over-etching. Wires become too thin and maybe disappear.
  * Under-etching. Wires may touch if placed too close together.
  * Misalignment of masks.
  * Wafer distortion due to high temperature steps.
  * Mask distortion.
    + Run out (accumulation of positioning errors.)
    + Glass flatness.
    + Magnification.
  * Focus (depth of field is about 5 microns.)
  * Differences in density of emulsion.
  * Differences in photoresist thickness.

Spice note.

  * Beware of a difference in the lithographic channel width
    from the actual, fabrication width.
  * Since transistor sizes as fabricated will vary from the
    layout, their behavior will vary as well!    
  * Spice has two factors, LD and WD, by which the specified
    length and width will be reduced during simulation.
      W       = W       - 2 * WD
       actual    layout
      L       = L       - 2 * LD
       actual    layout
  * LD and WD will usually be 0.5 and 0.3 of the minimum
    feature size, respectively.
      LD = lambda * 0.5
      WD = lambda * 0.3

Copyright (c) 1984 Paul J. Drongowski