VLSI systems #9 Speed, space and power trade-offs. P.J. Drongowski ****************** Power calculations ****************** Power distribution. * Power and ground must be distributed on metal. * The metal path are usually enmeshed: --------------------- | | | | | | | --------------------- because the paths cannot cross. * Fundamental limit on current per unit cross section of metal. * Metal migration. + Poorly understood. + If density threshold is exceeded, metal atoms physically move in the direction of the current. + Current is higher through constrictions in metal. + Eventually, a constriction will blow like a fuse! * For aluminum, maximum current density is about 2-3 mA/sq-micron. Conservative designers use a density of 1 mA/sq-micron. * For a minimum width metal wire of 3 lambda, lambda = 2 microns, and wire depth of 1, the current should be limited to: 3 lambda * 2 microns/lambda * 1 micron * 1 mA/sq-micron = 6 mA Subsystem power estimation. * Draw an inverter with W/L = 1/4 and W/L = 1/1. pu pd * Calculate the channel resistance from Vdd to ground, assuming that the input is ON. R = (4 + 1) * 10^4 ohms = 5 * 10^4 ohms * Let Vdd = +5V, then the current through the channel is: 5V I = ------------- = 0.1 mA 5 * 10^4 ohms * Therefore, a 3 lambda metal wire can power 60 inverters of this size. * 3 lambda power lines are only good for small subsystems. ************* Trading S/S/P ************* * Delay, transistor size and power consumption can all be traded against each other. W/L W/L W/L W/L W/L W/L pu pd pu pd pu pd --------------------------------------------- 1/4 1/1 1/2 2/1 1/1 4/1 --------------------------------------------- Delay 15/>60 ns 11/49 ns 9/16 ns Current 0.1 mA 0.2 mA 0.4 mA Rise and fall times are time required to go to minimum low and maximum high. 5V I = -------- = 0.1 mA long 5 * 10^4 5V I = ---------- = 0.2 mA wide 2.5 * 10^4 5V I = ----------- = 0.4 mA mid 1.25 * 10^4 -> Compute current and power (I * V) requirements for 10,000 and 100,000 gate systems. -> Describe the S/S/P optimization dilemma. * Need to drive long wire -> Make transistors bigger. * Change in layout makes wire shorter/longer -> Adjust transistor sizes. * Change makes power to big -> Make delays longer. * Etc. Why does nMOS consume a lot of power? Describe CMOS and switching time/power relationship. Copyright (c) 1984 Paul J. Drongowski