A follow-up on the Yamaha SWP51

Here’s a follow-up on the Yamaha SWP51 tone generator.

Sound On Sound (SOS) mentioned that the SWP51 tone generator was first used in the Yamaha Motif XS family. The Motif XS has two SWP51 ICs with a master/slave relationship. Each SWP51 has 8MBytes of dedicated DSP SDRAM. The two SWP51s share wave ROM arranged in two banks (high and low) of 512Mbits each for a total physical capacity of 128MBytes. Each wave ROM device is a Spansion S29GL512N10TFI020 which is a 32M by 16-bit parallel NOR flash memory. (Yay, Spansion. I ate lunch in their cafeteria in Austin.)

SOS and others claim that the SWP51 performs sample compression. The Yamaha specifications state wave ROM capacity at “355MBytes when converted to 16-bit linear format,” meaning uncompressed size. The waveforms are compressed in order to fit into 128MBytes of physical memory.

There is only one thing that we can conclude for sure. The PSR-S750 and PSR-950 have twice the physical wave ROM space as the Motif XS and MOX (256MBytes vs. 128MBytes).

The Motif XS with two SWP51s has 128 voice polyphony while the MOX has 64 voice polyphony. Thus, the MOX most likely has only one SWP51. The PSRs have 128 voice polyphony. If the later version of the SWP (SWP51L) has the same number of tone generating and DSP elements as the first version, then the arranger keyboards are deploying the elements differently than the Motif family instruments. Without knowing the internals of the SWP51 and its variants, this is pure speculation.

By the way, the main processor in the Motif XS is the Toshiba TX4939 RISC CPU. The CPU is clocked at 400MHz. The TX4939 is a MIPS architecture processor with several integrated I/O controllers and interfaces. The TX4939 is capable of generating an audio sampling clock and supports PCM input/output. The processor runs Monta Vista Linux. Yamaha has an equity stake in Monta Vista and distributes the GPL’ed source code three years after initial product release. Yamaha have not released source for the arranger keyboards, so most probably, the arrangers use a different embedded operating system.

The MIPS instruction set and the Renesas SH-4 instruction sets are not compatible. If the arranger and workstation product lines share software-level functionality, it must be at the source code level.

Just in case you aren’t confused enough already. The Tyros 3 has two SWP51B ICs and two SH-series CPUs (Renesas SH7727 SH-3-DSP main, and SH7206 SH-2A sub). The sub CPU handles the SWP51Bs while the main handles the user interface, etc. The microphone input is routed to one of the SWP51B ICs. Playback/record audio is routed from the other SWP51B to a gate array that interfaces to the hard drive subsystem. Wave ROM consists of four 512MBit mask ROM devices arranged in two banks for 256MBytes of total physical ROM. Tyros 3, by the way, was the first Tyros with Super Articulation 2 (SA2) voices.