VLSI systems

VLSI systems revolutionized the modern world!

The table below is the syllabus for an entry-level graduate course about VLSI systems and design. It was taken by senior-level undergraduates and first year graduate students. All were required to have a background in digital logic design. I taught this course for several years at Case Western Reserve University and once at Princeton University. Students were primarily from computer engineering and computer science.

The course used the Mead and Conway approach to VLSI systems and design. My goal was to train “tall, thin” designers who could specify system-level behavior and then translate that behavior into a testable transistor-level circuit and layout. Device physics and electronics were de-emphasized in order to focus on “system-oriented” issues and testing.

Students were allowed to choose their own projects. VLSI systems was taught in the Fall in order to submitted completed designs to the MOSIS fabrication service during the holiday break. Students could enroll in the Spring semester VLSI topics course, affording them the time and academic credit for testing their fabricated circuits. Circuits were tested using a Tektronix 9100 logic analyzer (now a museum piece). The 9100 had a basic programmable pattern generator as well as the usually digital analyzer. It was enough to get a taste of automated testing.

Students wrote high level models in C/C++. The high level model was translated to a datapath and control design at the register transfer level. A stylized C/C++ was used to model the datapath and control design. The register transfer level design was translated to a switching transistor net list and model. The datapath and control design were arranged into a floor plan consisting of modular building blocks. The building blocks were laid out in CMOS consistent with MOSIS design rules. Various generation, layout, rule checking, and simulation tools were employed: IRSIM, SPICE, etc.

Course overview
Linear Feedback Shift Registers
CMOS circuits
SPICE circuit-level simulation
CMOS fabrication process
CMOS design rules
Modularity, design, self-timed systems
System-level modeling
Speed, space and power estimation
Datapath synthesis
Example: Sum of array elements
IRSIM switch-level simulation
Netlist generation
Control and finite state machines
Automated synthesis
Introduction to testing
Structured testing
Tektronix 9100 logic analyzer
nMOS circuits

The VLSI systems course shares a few learning modules with the computer design course. The main difference is the amount of time devoted to these common topics. The VLSI systems course emphasized some topics (structured testing) while deemphasizing other topics (microprogramming). The essential methodology (writing, modeling and simulating at successively more detailed levels of representation) is the same in both courses.

SPICE was used for circuit-level modeling and simulation. Switch-level modeling and simulation was performed using IRSIM. IRSIM is still kicking around. We simulated fairly large, complex digital systems using IRSIM, so it is still a viable option for switch-level (logic) simulation. Students learned to embed building block designs into C/C++ language programs and then automatically generate either a SPICE or IRSIM netlist. This approach made it easy to generate the netlist for a large digital design while preserving building block modularity. Entries in the table below are links to SPICE, IRSIM and netlist examples.

Spice: 2 to 1 multiplexer
Spice: 16-bit ripple carry adder
Spice: D-type latch
IRSIM: 2 to 1 multiplexer
IRSIM: Transmission gate mux
IRSIM: 16-bit adder
IRSIM: 2-to-4 decoder
IRSIM: D-type latch
IRSIM: Content addressable memory
Netlist generation: 16-bit adder

The table below is the syllabus for an early version of the course using nMOS technology. The links point to lecture talking points. You can see that many of the ideas which are discussed in the (later) computer design, VLSI systems and computer architecture courses were already taking shape. Back in the day, we were using the ISP’ language — part of the N.mPc simulation system — for higher-level modeling. N.mPC was developed and spun-out by faculty and students at Case Western Reserve University.

System design space
Top-down design considerations
nMOS transistors
Circuit analysis and logic design
Steering logic; SPICE analysis
Silicon gate nMOS process
nMOS design rules and layout
Layout examples
Speed, space and power trade-offs
Building blocks
Architecture and methodology
ISP’ example: Cache memory
N.mPc organization-level descriptions
Self-timed systems
VLSI architecture and computation