Tag Archives: tone generation

Inside the DGX digital pianos

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Thanks to SeaGtGruff in the PSR Tutorial Forum, I took a chance to deep dive a few members of the Yamaha DGX portable grand family. The DGX is a “value” line of electronic keyboards offering a digital piano experience at affordable prices.

Polyphony depends on the available processing power and memory bandwidth (i.e., the ability to transfer samples from wave memory to the processing elements).

Here is a small table for some models in the DGX product line. I took a look at the service manual for models with distinctive features, e.g., DSP effects or no DSP effects. The analysis came out rather nice, so I decided to post it here, too.

           Poly Panel XGlite Kits REV CHO DSP IntMem  Processor
           ---- ----- ------ ---- --- --- --- ------  ------------------
DGX-200     32   108   480    12    8   4   0  352KB
DGX-300     32   122   480    12    8   4  38
DGX-500     32   122   480    12    8   4  38         HG73C205AFD SWX00B
DGX-520     32   127   361    12    9   4   0  875KB
DGX-530     32   127   361    12    9   4   0  875KB  YMW767-VTZ  SWL01T
DGX-620     32   127   361    12    9   4   0  875KB
DGX-630     64   130   361    12   29  24 182 1895KB
DGX-640     64   142   381    12   35  44 238 1895KB  R8A02032BG  SWX02
DGX-650    128   147   381    15   35  44 237  1.7MB  R8A02042BG  SWX08
DGX-660    192   151   388    15   41  44 237  1.7MB

Yamaha has several proprietary processors. The least powerful are the SWLs, which are normally used in the entry-level portables. The SWL does not have DSP support for variation/insert effects. Samples are transfered on the same bus as CPU instructions — low bandwidth. SWLs make for inexpensive products, but no DSP effects and relatively low polyphony.

The PSR E-series typically uses SWL01 variants such as the SWL01U in the PSR-E443. It’s interesting that the DGX members using the same SWL01 processor do not have DSP effects. The SWX processors have integrated DSP capability; the SWLs do not.

The SWX family of processors have dedicated buses/memories and a hardware digital signal processor for effects. (I deliberately avoided the acronym “DSP” here to avoid confusion with the way “DSP” is used in arranger terminology.) The SWX08 has three dedicated buses and memories:

  • SHA2 CPU bus and memory (CPU program and data)
  • Wave ROM bus and memory (voice samples)
  • DSP RAM bus and memory (working memory for digital signal processing)

The extra memory and external connections increase cost. However, this is a lot more processing power and memory bandwidth than the lowly SWL!

The SWX00 and SWX02 are earlier members of the family and aren’t used in new designs anymore. It’s too soon to see a service manual for the DGX-660, so any further comment is an educated guess. I suspect an SWX08 operating at a higher clock rate.

The SWX08 is used in the PSR-S750 and the SWX02 is used in the MOX. In both of these cases, the SWX is the main CPU and tone generation is handled by a single SWP51L tone generator chip, not the SWX. Because Yamaha had its own internal IC fab then these products were designed, Yamaha incorporated its own proprietary processor instead of an off-the-shelf Renesas R8. This is an effort to increase Yamaha’s own fab volume. Yamaha may even be using SWX chips in which the processor is good and the DSP is faulty and fused out!

Analysis isn’t complete without looking at wave memory size:

Model   Wave memory                Size         Description
------- -------------------------- ------------ ------------------------
DGX-500 K3N7V402GB-DC10            64Mbit  8MB  Mask ROM 64Mbit (wave)
DGX-530 Lapis Semi MR27V12852L     128Mbit 16MB 8Mx16b P2ROM (prog+wave)
DGX-640 Lapis Semi MR27V12852L     128Mbit 16MB 8Mx16b P2ROM (wave)
DGX-650 Spansion S29GL256S90TFI020 256Mbit 32MB 16Mx16b NOR flash (wave)

Memory size affects the number and quality of the voices. More memory allows more voices, more samples per voice, longer samples per voice, etc. Pianos are especially memory hungry. So, improvements in piano voices usually require significantly more wave memory. SWX wave memory is 16-bits, data parallel.

Now that Yamaha have sold off their IC fabrication capability, they aren’t under the same pressure to use proprietary processors. It’ll be interesting to see if Yamaha adopt ARM for tone generation and/or effects in value product lines. In the Reface line, they have adopted ARM for user interface and control. Yamaha’s Mobile Music Sequencer on iPad has a fairly completely XG engine, so Yamaha certainly aren’t strangers to tone generation on ARM!

If you enjoyed this article, you might also like this overview of the Tyros/PSR arranger family architecture.

Serial memory and tone generation

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Ah, September. Soon it will be time to speculate about new products at the Winter 2016 NAMM!

Every now and again, I take a pass through recent patent filings from Yamaha to get an idea about future product developments. Of course, the tech in a filing may never make it to product. However, a few common threads begin to appear over time.

This post starts with a patent application having the inauspicious title, “Sound Generation Apparatus.” This US application 2014/0123835 was filed on November 5, 2013 and is based on Japanese patent -244002, which was filed November 5, 2012.

First, a little background about the Yamaha tone generation architecture. Yamaha has used the same overall architecture for mid- and high-end workstations and tone modules since the mid-1990s. (TG-500, anyone?) These products employ one or more large scale integrated circuits for tone generation. Current versions of the tone generator IC, the SWP51L, has two dedicated memory channels for waveform data. Each channel has a 16-bit parallel data bus and a parallel address bus (24 or more bits wide). The parallel interface takes at least 40 pins per channel.

That’s a lot of incoming and outgoing connections (80 plus pins for both channels). IC packaging costs are in the range of $2.50 USD to $4.50 per pin. So, there is a direct relationship between the number of IC pins and manufacturing cost. Ultimately, this cost has a real effect on profit and the final price of the product.

The Yamaha patent application describes a serial interface for waveform memory in place of a parallel interface. The serial interface requires six pins per channel. Instead of 80 pins, the serial interface approach uses only 12, providing an 8 to 1 savings in packaging costs alone.

The application cites the Winbond 25Q series as the kind of flash memory to be supported by the serial interface. The largest 25Q device has a 64MByte capacity and can sustain a 40MByte/second transfer rate (quad SPI mode). This is nearly sufficient bandwidth to drive 128 44,100Hz stereo polyphonic voices (about 45MBytes/sec).

If you do the math that’s 128 times 44,100Hz times eight bytes. Two successive samples are required in order to perform interpolation although the oldest sample could be cached.

The product implications are interesting. At the low end of the scale (one or two channels), the device footprint is much smaller. The small size allows a corresponding decrease in the size of the product. Maybe a guitar pedal stomp box?

The high end of the scale is more intriguing. It becomes possible to build a tone generator IC with four or even eight independent channels of tone generation where each channel is driven by its own memory stream. We’re talking 1,024 polyphonic voices in the same LSI footprint as today’s SWP51L.

There are design implications for entry-level keyboard products, too. The SWL01 system on a chip (SOC) integrates both CPU and tone generator onto the same IC. Waveform data (samples) travel on the same bus as CPU instructions and data. A serial SPI interface requires only six pins and might let designers shift waveform storage from ROM on the system bus to a dedicated memory bus and channel. Software might be able to perform new tasks such as variation effects with more bandwidth available to the CPU on the system bus.

I feel confident to predict that the next generation of Standard Wave Processor (SWP) is in development. The SWP51L has been around for a while (including Tyros5). Here are a few key products and members of the SWP50 family:

    Product   Year  TG chip
    --------  ----  -------
    Tyros     2002  SWP50
    Motif XS  2007  SWP51
    Tyros 3   2008  SWP51B
    Tyros 5   2013  SWP51L

It is definitely time for a new design, not an incremental refresh.

Yamaha sees its internal integrated circuit capability as a strategic advantage. Up to this point, Yamaha have both designed and fabricated its own ICs. Last year, Yamaha transferred its fabrication line to Phenitec Semiconductor. Yep, Yamaha has gone fabless. This gets a huge capital expense off its balance sheet. It also means that Yamaha is under less pressure to reuse the same parts across product lines in order to get its IC manufacturing volume up. This is one reason why the SWP51 has had such long legs and why the SWL01 is used across all of the E-series arrangers. Volume, volume, volume! The pressure to (re)use Yamaha’s own IC solutions has been reduced.

We’ll see if Johnny can read (defenses) against Dick LeBeau. Go Browns!

Arranger memory: One more time!

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OK, OK, not everyone reads service manuals and schematics for their keyboard. However, I do get a little frustrated when posters compare apples to oranges, and make statements like “I can buy 1GByte for $1 (USD), so why is Yamaha so stingy with wave memory?”

Here is some information from the S750/S950 and Tyros5 service manuals and product data sheets. Please keep in mind that there are many different kinds of memory in an arranger. I’m going to focus on tone generation because that is the most relevant to wave memory size.

Both the S750/S950 and Tyros5 use proprietary Yamaha tone generator integrated circuits designated “SWP51L”. The S750/S950 designs use one SWP51L and the Tyros5 has two SWP51L chips. Each SWP51L has two dedicated memory ports (called “HIGH” and “LOW”) where each port consists of an address bus and a 16-bit parallel data bus.

In the S750/S950, each port is connected to a WAVE ROM:

    S750 WAVE ROM-L 1Gbit IC308   JS28F00AM29EWLA
    S750 WAVE ROM-H 1Gbit IC302   JS28F00AM29EWLA

That’s 128MBytes per device for a total of 256MBytes (2 times 128MBytes).

The Tyros5 microarchitecture is a little more complicated — the memory devices are shared between two SWP51Ls via separate shared address and data busses. There are six WAVE ROM integrated circuits:

    Tyros5 WAVE ROM-L0 1Gbit IC702   S29GL01GS10TFI020
    Tyros5 WAVE ROM-H0 1Gbit IC716   S29GL01GS10TFI020
    Tyros5 WAVE ROM-L1 1Gbit IC703   S29GL01GS10TFI020
    Tyros5 WAVE ROM-H1 1Gbit IC717   S29GL01GS10TFI020
    Tyros5 WAVE ROM-L2 1Gbit IC704   S29GL01GS10TFI020
    Tyros5 WAVE ROM-H2 1Gbit IC718   S29GL01GS10TFI020

That’s a total of 768MBytes (6 times 128MBytes).

Those cryptic names in the tables above identify the specific memory component. The components come from two vendors: Micro Technology and Spansion. Here are the gory details.

    Micron Technology JS28F00AM29EWLA  56-pin TSOP
        Parallel NOR Flash Embedded Memory
        Configurable width data bus (8- or 16-bits)
        Asynchronous random/page read
            Page access speed: 25ns
            Random access speed: 110ns
            Page size: 16 words or 32 bytes

    Spansion S29GL01GS10TFI020 56-bit TSOP

        GL-S MirrorBit Eclipse Flash Non-Volatile Memory
        S29GL01GS 1 Gbit (128 Mbyte)
        16-bit parallel data bus
        Asynchronous 32-byte page read
            Page access speed: 25ns
            Random access speed: 100ns
        Program and erase rates (i.e., write speed)
            Buffer Programming (512 bytes) 1.5 MB/s
            Sector Erase (128 kbytes) 477 kB/s

The read speed (25ns per 16-bit word in page mode) is much faster than write speed, and that’s OK in this application because the data is always read once it’s loaded/initialized. The SWP51L probably operates in page mode since the samples are accessed sequentially. Dunno ’bout you, but 25 nanoseconds per 16-bit word is darned fast. The access speed is MUCH higher than a typical USB flash drive.

Two 27-bit address busses and two 16-bit data busses are sent to/from the plug-in expansion board. These busses extend the two shared WAVE ROM busses. The expansion board needs to keep up with the high read rate.

Please note that the CPU does not get anywhere near the sample streams. That work is assigned to the SWP51Ls.

Hope this helps to clarify.