Tag Archives: courseware

Topics in computer architecture

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A new courseware page — topics in computer architecture — is now available. This page covers a wide mix of topics from RISC vs. CISC to non-von Neumann languages and architectures. You might just find an interesting lecture or two for a special topics seminar about computer architecture.

Way back when in the early eighties, I had a chance to work with Al Davis at the University of Utah. Al was a proponent of data-driven dataflow computers. His ideas showed me that there are alternatives to centralized synchronous control, sequential programming and the von Neumann memory bottleneck. The topics page has links to information about some of this interesting work.

Looking back, I’m struck at how mired we are in the von Neumann architecture! Sure, there are a few projects underway to investigate alternatives like quantum computing, functional programming languages, and so forth. However, the world remains dominated by the centralized, sequential von Neumann model and programming languages in which parallelism is glued on through a (class) library or two. General purpose GPU (GPGPU) computation is not really that radical. Yes, GPGPU computation is data parallel, but the underlying model is the sequential execution of SIMD instructions. Speculative execution is a bit of a kludge to allow conditional execution in highly sequential SIMD programs. Further, data transfer from memory to execution units remains a limiting factor in performance.

I think we need to introduce students to a wide range of computing models. Hopefully, some young, clever soul will find a way to pull us out of our rut!

VLSI systems course

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The syllabus and notes for my VLSI systems course is now available in the courseware section of the site.

This is a “Mead and Conway” course on VLSI systems and CMOS circuit design. Mead and Conway led the world with their approach to VLSI design. Instead of focusing on device electronics and physics, this approach spans system-level design down to layout and fabrication. It is particularly well-suited for computer science majors who may not have much background in electronics.

I approach VLSI system design like computer design. Heck, a computer is just another digital system to be implemented in CMOS! Thus, students build and test a series of successively more detailed models for a VLSI (digital) system, eventually implementing a circuit layout which is suitable for fabrication. At the time, student designs were manufactured by the MOSIS fabrication service (which is still in business, by the way).

Both the computer design and VLSI systems courses relied quite heavily on simulation. System- and register transfer-level models were written in a stylized C/C++. Logic- and switching transistor-level simulation was handled by IRSIM. Electronic circuit-level simulation was performed through SPICE. It’s good to see that IRSIM is open source and is still available. And, of course, SPICE is still an industry standard.

Most academic courses have switched to VHDL or Verilog for system- and register transfer-level modeling. Both languages and associated simulators can be applied to the logic-level, too. I would strongly consider or recommend either option today. Depending upon tool support, students may also be able to synthesize their designs in field programmable gate array (FPGA) technology. Logisim and SmartSim look like terrific alternatives, too. I saw a LogiSim demo at SIGCSE last March and it’s a pretty spiffy tool. SmartSim runs on the Raspberry Pi — what could be better than that?

Unfortunately, VHDL and Verilog are not the most approachable, easily understood languages. I’m not the only person with this opinion. Please see “FPGA Programming for the Masses” in the April 2013 issue of CACM. I’ve seen advertising that calls Verilog “C-like.” I disagree.

My ulterior motive is to reach and teach digital systems at the high school level. VHDL and Verilog, unfortunately, are not as easily learned as C/C++ or Java. I’m hoping to gain more hands-on experience when I get rolling with Papillio — maybe find a way to bridge Java/C/C++ to VHDL and open the door to a broader community of students.