Tag Archives: architecture

SSP1 and SSP2: Designated hitter

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One notable absence from the Yamaha PSR-S970 design is the “SSP2” integrated circuit (IC) which handles vocal harmony processing. The SSP1 and SSP2 appeared in the Tyros series and PSR series coincident with Vocal Harmony 2.

For you signal sleuths, the PSR-S950 and Tyros 5 microphone input is routed to an analog-to-digital converter (ADC) where the analog signal is sampled and digitized. The digital sample stream is sent to the SSP2 IC. The firmware munges on the samples and voila, the SSP2 produces a vocal harmony signal that is mixed with samples from the tone generator, etc. The SSP2 sends its results to the TG where effects and mixing are performed. The TG sends its output to the digital-to-analog converters (DAC) and digital amplifiers. The Tyros 4 has the same signal flow using an earlier model “SSP1” processor instead.

Previous machines with vocal harmony (e.g., Tyros 3 and earlier, PSR-S910 and earlier), routed the digitized microphone stream to a tone generator (TG) IC such as the SWP51L. Presumably, vocal harmony processing was performed in the TG IC. With the brand new SWP70 tone generator in the S970, the digitized microphone stream is sent to the SWP70. Looks like vocal harmony processing is folded into the SWP70 TG.

I didn’t give the SSP2 much thought or investigation, and just assumed that it was a gate array or something. On inspection, the pin-out resembles a Renesas embedded DSP processor with analog inputs and outputs, digital I/O, USB and all of the usual suspects. The SSP2 in the S950 has 2MBytes of NOR flash program ROM (organized 1Mx16bits) and 2MBytes of SDRAM (organized 1Mx16bits). The clock crystal is a leisurely 12.2884MHz although the SDRAM read clock is 84.7872MHz.

Mysteriously, a web search on the part numbers doesn’t turn up much information. The part numbers are:

    Schematic ID  Manufacturer?       Yamaha
    ------------  ------------------  --------
    SSP1          MB87S1280YHE        X6363A00
    SSP2          UPD800500F1-011-KN  YC706A0

The PSR-S950 parts list does not give a Yamaha order number for the SSP2. If the SSP2 fails, you’ll need to call Yamaha 24×7 directly.

A web search does turn up a few of the interesting places where the SSP has been seen. In addition to Tyros 4, Tyros 5 and S950, the SSP and SSP2 are featured in:

    PSR-S500 arranger (probable role: effects processor)
    EMX5016CF mixer (role: SPX effects and user interface)
    Steinberg UR22 audio interface
    Steinberg MR816 Firewire audio interface
    Yamaha THR modeling guitar amplifier

The SSP is Yamaha’s designated hitter when they need an odd bit of DSP work done.

Arranger memory: One more time!

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OK, OK, not everyone reads service manuals and schematics for their keyboard. However, I do get a little frustrated when posters compare apples to oranges, and make statements like “I can buy 1GByte for $1 (USD), so why is Yamaha so stingy with wave memory?”

Here is some information from the S750/S950 and Tyros5 service manuals and product data sheets. Please keep in mind that there are many different kinds of memory in an arranger. I’m going to focus on tone generation because that is the most relevant to wave memory size.

Both the S750/S950 and Tyros5 use proprietary Yamaha tone generator integrated circuits designated “SWP51L”. The S750/S950 designs use one SWP51L and the Tyros5 has two SWP51L chips. Each SWP51L has two dedicated memory ports (called “HIGH” and “LOW”) where each port consists of an address bus and a 16-bit parallel data bus.

In the S750/S950, each port is connected to a WAVE ROM:

    S750 WAVE ROM-L 1Gbit IC308   JS28F00AM29EWLA
    S750 WAVE ROM-H 1Gbit IC302   JS28F00AM29EWLA

That’s 128MBytes per device for a total of 256MBytes (2 times 128MBytes).

The Tyros5 microarchitecture is a little more complicated — the memory devices are shared between two SWP51Ls via separate shared address and data busses. There are six WAVE ROM integrated circuits:

    Tyros5 WAVE ROM-L0 1Gbit IC702   S29GL01GS10TFI020
    Tyros5 WAVE ROM-H0 1Gbit IC716   S29GL01GS10TFI020
    Tyros5 WAVE ROM-L1 1Gbit IC703   S29GL01GS10TFI020
    Tyros5 WAVE ROM-H1 1Gbit IC717   S29GL01GS10TFI020
    Tyros5 WAVE ROM-L2 1Gbit IC704   S29GL01GS10TFI020
    Tyros5 WAVE ROM-H2 1Gbit IC718   S29GL01GS10TFI020

That’s a total of 768MBytes (6 times 128MBytes).

Those cryptic names in the tables above identify the specific memory component. The components come from two vendors: Micro Technology and Spansion. Here are the gory details.

    Micron Technology JS28F00AM29EWLA  56-pin TSOP
        Parallel NOR Flash Embedded Memory
        Configurable width data bus (8- or 16-bits)
        Asynchronous random/page read
            Page access speed: 25ns
            Random access speed: 110ns
            Page size: 16 words or 32 bytes

    Spansion S29GL01GS10TFI020 56-bit TSOP

        GL-S MirrorBit Eclipse Flash Non-Volatile Memory
        S29GL01GS 1 Gbit (128 Mbyte)
        16-bit parallel data bus
        Asynchronous 32-byte page read
            Page access speed: 25ns
            Random access speed: 100ns
        Program and erase rates (i.e., write speed)
            Buffer Programming (512 bytes) 1.5 MB/s
            Sector Erase (128 kbytes) 477 kB/s

The read speed (25ns per 16-bit word in page mode) is much faster than write speed, and that’s OK in this application because the data is always read once it’s loaded/initialized. The SWP51L probably operates in page mode since the samples are accessed sequentially. Dunno ’bout you, but 25 nanoseconds per 16-bit word is darned fast. The access speed is MUCH higher than a typical USB flash drive.

Two 27-bit address busses and two 16-bit data busses are sent to/from the plug-in expansion board. These busses extend the two shared WAVE ROM busses. The expansion board needs to keep up with the high read rate.

Please note that the CPU does not get anywhere near the sample streams. That work is assigned to the SWP51Ls.

Hope this helps to clarify.