As I mentioned in an earlier post, the Yamaha PSR-S770 and PSR-S970 arranger workstations have a new tone generator (TG) integrated circuit (IC) — the SWP70. (“SWP” stands for “Standard Wave Processor.”) The SWP70 is a new TG family in a long line of Yamaha tone generators. The SWP70 replaces the SWP51L, which has been the mainstay in recent generations of Tyros, upper range PSR, Motif, and MOX series workstations.
The SWP70 has much in common with the SWP51L, but also some very significant differences. The SWP70’s external clock crystal frequency is 22.5792 MHz versus 11.2896 MHz for the SWP51L. This funky looking clock rate is a multiple of 44,100 Hz:
22.5792MHz = 44,100Hz * 512
Samples are transferred to the DAC, etc. at a multiple of 44,100 Hz (Fs). Thus, it makes sense to derive Fs and its multiples from the chip-level master clock. The higher crystal frequency and faster memory read clocks lead me to believe that the SWP70 is clocked twice as fast as the SWP51L.
I am comparing SWP characteristics as deployed in the S970 (SWP70) and the S950 (SWP51L) workstations. This keeps the basis of comparison even although many characteristics (clock rates, DSP RAM size) are the same in higher end models like Tyros 5 or Motif. Higher end models employ two SWPs in master/slave relationship and both SWPs share the same wave memory. For more information about the PSR-S970 internal design, look here.
Five interfaces are essentially the same as the SWP51L:
- CPU interface: Communicate with the Main CPU (e.g., Renesas SH7731) via the parallel CPU bus.
- Serial audio: Send/receive audio data to/from the DAC, audio ADCs, and main CPU.
- Clock interface: Synchronize serial audio data transfers (generate multiples of Fs).
- DSP SDRAM interface: Store working data for effect processing.
- EBUS interface: Receive controller data messages (e.g., pedal input, keyboard input, pitch bend, modulation, live knobs, etc.) from front panel processors.
The DSP SDRAM is the same size: 4Mx16bits (8MBytes). The SWP70 read clock is 95.9616 MHz, while the SWP51L read clock is 45.1584 MHz. This is more evidence for a higher internal clock frequency.
The Tyros 4, Tyros 5 and S950 have an auxiliary DSP processor for vocal harmony. The microphone analog-to-digital (ADC) converter is routed directly to the auxiliary processor. Prior to these models, the microphone ADC is connected to the tone generator. With the SWP70, the S970’s microphone ADC is once again routed to the SWP70 and the auxiliary processor disappears from the design. Thus, vocal harmony processing (fully or partially) is located in the SWP70. See my post about SSP1 and SSP2 for further details.
The biggest change is the wave memory interface.
A little history is in order. The SWP51L (and its ancestors) were designed in the era of mask programmable ROM. I contend that tone generation is memory bandwidth limited and the earlier interface design is driven by the need for speed. The SWP51L (due to its evolved history) has two independent wave memory channels (HIGH and LOW). Each channel has a parallel address bus (32 bits) and a parallel data bus (16 bits). The two channels account for over 100 pins. (System cost is proportional to pin count.) The user-installed, 512/1024MB flash DIMMs plug directly onto the two channels.
The SWP70 wave memory interface takes advantage of new NAND flash memory technology. The interface is described in US patent application 2014/0123835 and is covered by Japanese patent 2012-244002. I analyzed the US patent application in an earlier post.
The SWP70 retains the HIGH port and LOW port structure. Each port communicates with an 8Gbit Spansion S34ML08G101TFI000 NAND flash device. Address and data are both communicated over an 8-bit serialized bus. This technique substantially decreases pin count and the resulting board-/system-level costs. Smart work.
I did not anticipate, however, the introduction of a new parallel memory interface called “wave-work”. The wave work interface communicates with a 16Mx16bit (32MBytes) Winbond W9825G6JH-6 SDRAM. The read clock is 95.9616 MHz.
The purpose of the wave work SDRAM is revealed by US Patent 9,040,800. This patent discloses a compression algorithm that is compatible with serialized access to the wave memory. The wave work SDRAM is a cache for compressed samples. The characteristics of the Spansion memory device give us a clue as to why a cache is required:
Block erase time 3.5ms Horrible (relative to SDRAM) Write time 200us Terrible Random access read time 30us Bad Sequential access read time 25ns Very good
As the patent explains, two (or more) samples are required to perform the interpolation while pitch-shifting. If there is only one tone generation channel, access is paged sequential. However, random access is required when there are multiple tone generation channels. (The patent mentions 256 channels.) Each channel may be playing a different voice or a different multi-sample within the same voice. One simply cannot sustain high polyphony through random access alone. The cache speeds up access to recently used pages of uncompressed samples.
The wave work interface takes additional pins, thus adding to board- and system-level costs. The overall pin count is still lower when compared to SWP51L. The penalty must be paid in order to use contemporary NAND flash devices with a serialized bus. This is the price for catching the current (and future) memory technology curve.
A few SWP70-related printed circuit board (PCB) positions are unpopulated (i.e., IC not installed) in the PSR-S970. There is an unpopulated position for a second Winbond W9825G6JH-6 wave work SDRAM which would expand the wave work memory to 32Mx16bit (64MBytes). A larger cache would be needed to support additional tone generation channels. Perhaps only half of the tone generation channels are enabled in the mid-grade PSR-S970 workstation.
There is what appears to a second separate wave work interface that is completely unpopulated. The intended memory device is a Winbond W9825G6JH-6, which is consistent with the existing wave work interface.
The PSR-S970 also has a stubbed out interface that is similar to the DSP SDRAM interface. The existing DSP SDRAM signals are labeled “H” for HIGH while the unused interface is labeled “L” for LOW. Perhaps only half of the hardware DSP processors are enabled for the mid-grade S970, waiting to be activated in future high-end Tyros and Motif products.
I refer to future high end products by the names of the current product lines. Yamaha may choose to rebrand future products (e.g., the much-rumored “Montage” trademark).
The Spansion S34ML08G2 8-Gb NAND device is Open NAND Flash Interface (ONFI) 1.0 compliant. The S34ML08G2 device is a dual-die stack of two S34ML04G2 die. The 8-bit I/O bus is tri-state allowing expansion e.g., multiple memory devices sharing the same I/O bus and control signals with at most device enabled at any time. The SWP70 has additional chip select pins that would support this kind of expansion. The current expansion flash DIMMs will no longer be needed or used.
In this note, I concentrated on observations and fact, not speculation about future products. I’ll leave that fun for another day!
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